1. Field of the Invention
The present invention relates to a level down converter, especially having two inverters.
2. Description of the Related Art
Conventionally, attempts have been done to have internal circuits operate with a low power supply voltage, to reduce the power consumption of semiconductor integrated circuits, while maintaining the voltage level of input/output signals with external. In such semiconductor integrated circuits, a level down converter, with inverters which consist of thick oxide film transistors having thick gate oxide films on input portions thereof, is provided.
FIG. 7 is a view which shows circuits of a level down converter according to a prior art. A front stage inverter has MOS field effect transistors 701a and 702a, and a rear stage inverter has MOS field effect transistors 703a and 704a. Hereinafter, these MOS field effect transistors will be referred to as MOS transistors.
At first, the front stage inverter is described hereafter. To an input terminal Vin, a gate of a p-channel MOS transistor 701a and a gate of a n-channel MOS transistor 702a are connected. A source of the p-channel MOS transistor 701a is connected to a high power supply voltage Vdde (for example, 3.3 V), and a drain thereof is connected to a node V2. A source of the n-channel MOS transistor 702a is connected to a reference potential Vsse (for example, 0 (zero) V), and a drain thereof is connected to the node V2. This front stage inverter, as shown in FIG. 8, inputs digital signals (for example, clock signals) of, for example, from 0 (zero) V to 3.3 V, which are inputted to the input terminal Vin, and outputs signals which are made by logical inversions of the signals to the node V2. The signals of the node V2 are also signals of, for example, from 0 (zero) V to 3.3 V.
Operations of the front stage inverter are described. When the input terminal Vin is in low level (0 V), (during the times t2 to t3), the p-channel MOS transistor 701a is turned on, and the n-channel MOS transistor 702a is turned off. As a result, the node V2 becomes high level (3.3 V). On the contrary, when the input terminal Vin is in high level (3.3 V) (during the times t1 to t2, and t3 to t4), the p-channel MOS transistor 701a is turned off, and the n-channel MOS transistor 702a is turned on. As a result, the node V2 becomes low level (0 V).
Next, the rear stage inverter is described hereafter. To the node V2, a gate of a p-channel MOS transistor 703a and a gate of a n-channel MOS transistor 704a are connected. A source of the p-channel MOS transistor 703a is connected to a low power supply voltage Vdd (for example, 1.2 V), and a drain thereof is connected to an output terminal Vout. A source of the n-channel MOS transistor 704a is connected to a reference potential Vss (for example, 0 (zero) V), and a drain thereof is connected to the output terminal Vout. This rear stage inverter, as shown in FIG. 8, inputs digital signals of the node V2 of, for example, from 0 (zero) V to 3.3 V, and outputs signals which are made by logical inversions of the signals to the output terminal Vout. The signals of the output terminal Vout are signals of, for example, from 0 V to 1.2 V. The start-up speed of this signals of the output terminal Vout becomes slow. The reason will be described later.
Operations of the rear stage inverter are described. When the node V2 is in low level (0 V)(during the times t1 to t2, and t3 to t4), the p-channel MOS transistor 703a is turned on, and the n-channel MOS transistor 704a is turned off. As a result, the output terminal Vout becomes high level (1.2 V). On the contrary, when the node V2 is in high level (3.3 V)(during the times t2 to t3), the p-channel MOS transistor 703a is turned off, and the n-channel MOS transistor 704a is turned on. As a result, the output terminal Vout becomes low level (0 V).
The power supply voltage Vdde (3.3 V) of the front stage inverter is high, and the power supply voltage Vdd (1.2 V) of the rear stage inverter is low. Digital signals from 0 V to 3.3 V are inputted to the input terminal Vin, so the gate oxide films of the MOS transistors 701a and 702a are required to be thick, in order to prevent the gate oxide films of the MOS transistors 701a and 702a from being broken.
And signals of the node V2 are also from 0 V to 3.3 V, so the gate oxide films of the MOS transistors 703a and 704a are required to be thick, in order to prevent the gate oxide films of the MOS transistors 703a and 704a from being broken.
A level down converter capable of preventing the decrease of an operating speed, and reducing power consumption by reducing the increase of through currents is described in Japanese Patent Application Laid-open No. 2002-246893.
As shown in FIG. 8, the reason why the start-up speed of signals of the output terminal Vout becomes slow, is described. When the p-channel MOS transistor 703a is applied 0 (zero) V to the gate thereof, the transistor 703a is turned on, and the current Ids flows between the source and the drain thereof. This current Ids becomes large as the absolute value of the voltage Vgs of the gate to the source thereof becomes high. When the gate is applied 0 (zero) V, the voltage Vgs becomes −1.2 V.
It is also required to consider a threshold voltage of the transistor 703a. In the transistor 703a, the current Ids flows when the voltage Vgs is on or less than a negative threshold voltage. So actually, the current Ids flows in accordance with the voltage which is found by subtracting the negative threshold voltage from the voltage Vgs (−1.2 V). To be more specific, as the absolute value of the threshold voltage becomes low, a large current Ids flows. The absolute value of the threshold voltage of a transistor having a thick gate oxide film is high compared to that of a transistor having a thin gate oxide film. Therefore, the current Ids becomes small, and the operation speed of the transistor 703a becomes slow. As a result, the start-up speed of the output terminal Vout in FIG. 8 becomes slow. To be more specific, the transition time of the output terminal Vout to change the voltage from 0 (zero) V to 1.2 V becomes slow.
On the contrary, the start-down speed of the output terminal Vout does not become slow. When a n-channel MOS transistor 704a is applied 3.3 V to a gate thereof, the transistor 704a is turned on, and the current Ids flows between a drain and a source thereof. This current Ids becomes large as the voltage Vgs of the gate to the source becomes high. When the gate is applied 3.3 V, the voltage Vgs becomes high voltage of 3.3 V. As the voltage Vgs is a high voltage, the current Ids becomes large, and the operation speed of the transistor 704a becomes fast. As the turn-on operation speed of the transistor 704a is fast, the start-down speed of the output terminal Vout in FIG. 8 becomes fast. To be more specific, the transition time of the output terminal Vout to change the voltage from 1.2 V to 0 (zero) V becomes fast.
As the start-up speed of the signals of the output terminal Vout becomes slow, the duty ratio deteriorates. To be more specific, a high level period 811 of the output terminal Vout becomes short compared to a high level period 801 of the input terminal Vin, and a low level period 812 of the output terminal Vout becomes long compared to a low level period 802 of the input terminal Vin.
Either high level or low level of the signals of the output terminal Vout is determined by a threshold value 810 as a basis. The output signals have the slow start-up speed, so the transition timing from low level to high level is sensitive and easy to be shifted. The reason for this is because the absolute value of the voltage Vgs which is applied to the p-channel MOS transistor 703a is low, so it operates in the sub-threshold region, and the characteristic becomes unstable. When a characteristic dispersion between the p-channel MOS transistor and the n-channel MOS transistor is large, the duty ratio of the output signals tends to be deteriorated. And, when noise on the power supply or on the ground is generated, the output signals tend to be deteriorated.
When high frequency clock signals are inputted to the input terminal Vin, the p-channel MOS transistor 703a has the slow operation speed, therefore clock signals can not be outputted or the duty ratio of output clock signals may be deteriorated. When the power supply voltage Vdd becomes lower, level conversions of signals become hard.